56
9140CINDCO02/10
ATA8741
Figure 16-1. Reset Logic
16.0.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in System and Reset Characterizations on page 198. The POR is activated when-
ever V
CC
is below the detection level. The POR circuit can be used to trigger the Start-up Reset,
as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC
rise. The RESET signal is activated again, without any delay,
when V
CC
decreases below the detection level.
Figure 16-2. MCU Start-up, RESET
Tied to V
CC
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [1..0]
Delay Counters
CKSEL[1:0]
CK
TIMEOUT
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
SUT 1:0
Power-on Reset
Circuit
RESET
IME-OUT
NTERNAL
RESET
t
TOUT
V
RST
V
PORMA X
CC
CCRR
V
V
PORMIN
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